2015
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IEEE CAL
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Our vision for what a next-generation exascale-class computing system should look like:
a large network of journaled non-volatile, NAND-flash, main-memory nodes.
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IEEE CAL
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Our vision for what a next-generation exascale-class compute node should look like.
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2013
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HPCA
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One of the hallmarks of large-scale systems is large last-level caches, and it is surprising
what the trade-offs look like -- you end up choosing technologies you would not have expected.
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ITJ
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"An integrated simulation infrastructure for the entire memory hierarchy: Cache, DRAM, nonvolatile
memory, and disk."
J. Stevens, P. Tschirhart, M.-T. Chang, I. Bhati, P. Enns, J. Greensky, Z. Chishti, S.-L. Lu, and B.
Jacob. Intel Technology Journal, vol. 17, no. 1. 2013.
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This describes the simulation environment for our non-volatile main memory systems.
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2012
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[HMC]
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This describes our work for Micron during their development of the Hybrid Memory Cube DRAM.
Paul and Elliott did the performance modeling for several years. When Micron announced the
DRAM in 2012, we were finally able to write up what we had done. This is the part we can talk about. :)
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ISCA
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"Buffer On Board memory systems."
Elliott Cooper-Balis, Paul Rosenfeld, and Bruce Jacob.
Proc. 39th International Symposium on Computer Architecture (ISCA 2012), pp. 392-403.
Portland OR, June 2012.
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A whole lot of high-performance servers use this architecture today ... it has become one of the
staples in high-capacity memory design.
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2010
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[NVMM]
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"A journaled, NAND-flash main-memory system."
B. Jacob, I. Bhati, M.-T. Chang, P. Rosenfeld, J. Stevens, P. Tschirhart, Z. Chishti, S.-L. Lu, J. Ang,
D. Resnick, and A. Rodrigues.
University of Maryland Systems and Computer Architecture Group Technical Report UMD-SCA-2010-12-01.
December 2010 (some references updated 2014).
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This is what next-generation memory systems are going to look like.
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2009
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MoBS
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We started looking at CMP issues a long time ago ...
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Morgan
Claypool
book
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Since 2008 (when I had finished writing this book and it was being sent around to reviewers)
we have been telling people that the main memory needs to be made out of flash instead of
DRAM.
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2008
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TECS
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Being able to simulate large systems means you have to be able to simulate things extremely fast.
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2007
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(book)
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Memory Systems: Cache, DRAM, Disk.
Bruce Jacob, Spencer W. Ng, and David T. Wang, with contributions by Samuel Rodriguez.
ISBN 978-0-12-379751-3.
Morgan Kaufmann Publishers, Fall 2007.
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This represents the culmination of much of our work in memory systems.
Currently sitting at about 1000 pages, densely set (~500 words per page), it is roughly
half a million total words.
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HPCA
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2006
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ISLPED
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This is the most accurate study of SRAM energy & power yet; Sam's software, vCACTI, is a
major overhaul of existing CACTI-based programs.
Read his thesis.
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HPCA
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Few besides Aamer are really looking at what sort of sharing patterns exist in the last-level cache.
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2005
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HPCA
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The funny thing about out-of-order execution is that it is great for general instructions, but it
is sucky for memory instructions. Norm Jouppi was one of the first to notice this, and
Aamer was his intern at the time ... Norm handed the idea off to Aamer, and the study was born.
Took us several years to get people to believe the results.
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ISPASS
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A really cool set of benchmarks that pounds the memory system.
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SIGARCH
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"DRAMsim: A memory-system simulator."
David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Katie Baynes, Aamer Jaleel, and Bruce Jacob.
SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 100-107. September 2005.
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Simply put, the most accurate DRAM system simulator in the world. At least, that we know of.
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2004
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ISCA
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We started looking at VLIW issues a long time ago ...
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2003
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IEEE Micro
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This is really the publication that got us into supercomputer design. Because of this paper,
researchers at Cray reached out to us; and so we designed their Black Widow memory controller.
Then we were invited to start participating in DOE supercomputer design processes.
Later, like the work for Cray, Micron reached out to us to help them design the Hybrid Memory Cube.
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