Selected Publications of the Maryland DSP-CAD Research Group
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invoked by each author's copyright.
A BibTeX file containing bibliographic
information for all publications listed here is also available.
Globally, this publication list is ordered in reverse chronological
order. Within a given year, the ordering is alphabetical (by author
name).
We are grateful to the following sponsors, who have supported
the research reported in these publications and research in
the Group at large:
Agilent Technologies, Angeles Design Systems, Inc.;
the Defense Advanced Research Projects Agency;
the Department of Defense Maryland Procurement Office;
National Instruments;
Northrop Grumman Corp.; the Semiconductor Research Corporation;
Trident Systems, Inc.;
the University of Maryland Graduate School;
the US Army Research Laboratory; and
the US National Science Foundation.
DSP-CAD Group Students.
Research in the DSP-CAD Group is directed by
Professor Shuvra S. Bhattacharyya.
Publications are listed for the following years:
2006, 2005, 2004, 2003, 2002, 2001, 2000, 1999, 1998, 1997, 1996, 1995, 1994, 1993
Bibliography generated from contents-in.bib
- [bhat2006x2]
- S. S. Bhattacharyya and W. S.
Levine.
Optimization of signal processing software for control system implementation.
In Proceedings of the IEEE Symposium on Computer-Aided Control Systems
Design, Munich, Germany, October 2006.
Invited paper.
(PDF)
- [bhat2006x1]
- S. S. Bhattacharyya and W. Wolf.
Tools and methodologies for system-level design.
In L. Scheffer, L. Lavagno, and G. Martin, editors, Electronic Design
Automation for Integrated Circuits Handbook --- Volume 1: EDA for IC
System Design, Verification, and Testing, pages 3-1-3-19. Taylor &
Francis Group, 2006.
(PDF)
- [depr2006x1]
- E. F. Deprettere, T. Stefanov,
S. S. Bhattacharyya, and M. Sen.
Affine nested loop programs and their binary cyclo-static dataflow
counterparts.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, Steamboat Springs, Colorado,
September 2006.
(PDF)
- [haim2006x1]
- F. Haim, M. Sen, D. Ko, S. S.
Bhattacharyya, and W. Wolf.
Mapping multimedia applications onto configurable hardware with parameterized
cyclo-static dataflow graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages III-1052-III-1055, May 2006.
(PDF)
- [hsu2006x1]
- C. Hsu, S. Ramasubbu, M. Ko, J. L.
Pino, and S. S. Bhattacharyya.
Efficient simulation of critical synchronous dataflow graphs.
In Proceedings of the Design Automation Conference, pages
893-898, San Francisco, California, July 2006.
(PDF)
- [khan2006x1]
- M. Khandelia, N. K. Bambha, and
S. S. Bhattacharyya.
Contention-conscious transaction ordering in multiprocessor DSP systems.
IEEE Transactions on Signal Processing, 54(2):556-569, February
2006.
(PDF)
- [kian2006x2]
- V. Kianzad.
System Synthesis for Embedded Multiprocessors.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [kian2006x1]
- V. Kianzad and S. S.
Bhattacharyya.
Efficient techniques for clustering and scheduling onto embedded
multiprocessors.
IEEE Transactions on Parallel and Distributed Systems,
17(7):667-680, July 2006.
(PDF)
- [ko2006x5]
- D. Ko.
System Synthesis for Image Processing Applications.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [ko2006x4]
- M. Ko.
Integrated Software Synthesis for Signal Processing Applications.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [ko2006x2]
- D. Ko, C. Shen, S. S. Bhattacharyya,
and N. Goldsman.
Energy-driven partitioning of signal processing algorithms in sensor networks.
In International Workshop on Embedded Computer Systems: Architectures,
Modeling, and Simulation, Lecture Notes in Computer Science 4017,
pages 142-154. Springer, Samos, Greece, July 2006.
(PDF)
- [ko2006x1]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Beyond single appearance schedules: efficient DSP software synthesis using
recursive procedure calls.
ACM Transactions on Design Automation of Electronic Systems, 2006.
To appear.
(PDF)
- [ko2006x3]
- M. Ko, C. Shen, and S. S.
Bhattacharyya.
Memory-constrained block processing optimization for synthesis of DSP
software.
In Proceedings of the International Conference on Embedded Computer
Systems: Architectures, Modeling, and Simulation, pages 137-143,
Samos, Greece, July 2006.
To appear.
(PDF)
- [ko2006x6]
- M. Ko, C. Zissulescu,
S. Puthenpurayil, S. S. Bhattacharyya, B. Kienhuis, and E. Deprettere.
Parameterized looped schedules for compact representation of execution
sequences.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, Steamboat Springs, Colorado,
September 2006.
(PDF)
- [murt2006x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Memory Management for Synthesis of DSP Software.
CRC Press, 2006.
(PDF)
- [teic2006x1]
- J. Teich and S. S. Bhattacharyya.
Analysis of dataflow programs with interval-limited data-rates.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 43(2-3):247-258, June 2006.
(PDF)
- [bamb2005x1]
- N. Bambha and S. S. Bhattacharyya.
Joint application mapping/interconnect synthesis techniques for embedded
chip-scale multiprocessors.
IEEE Transactions on Parallel and Distributed Systems,
16(2):99-112, February 2005.
(PDF)
- [bamb2005x2]
- N. K. Bambha and S. S.
Bhattacharyya.
Communication strategies for shared bus embedded multiprocessors.
In Proceedings of the International Workshop on Embedded Software,
pages 21-24, Jersey City, New Jersey, September 2005.
(PDF)
- [hsu2005x3]
- C. Hsu and S. S. Bhattacharyya.
Integrating VSIPL support in the dataflow interchange format.
In Proceedings of the Annual Workshop on High Performance Embedded
Computing, pages 75-76, Lexington, Massachusetts, September 2005.
(PDF)
- [hsu2005x1]
- C. Hsu and S. S. Bhattacharyya.
Porting DSP applications across design tools using the dataflow interchange
format.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 40-46, Montreal, Canada, June 2005.
(PDF)
- [hsu2005x2]
- C. Hsu, M. Ko, and S. S.
Bhattacharyya.
Software synthesis from the dataflow interchange format.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 37-49, Dallas, Texas, September 2005.
(PDF)
- [kian2005x2]
- V. Kianzad, S. Saha,
J. Schlessman, G. Aggarwal, S. S. Bhattacharyya, W. Wolf, and R. Chellappa.
An architectural level design methodology for embedded face detection.
In Proceedings of the International Conference on Hardware/Software
Codesign and System Synthesis, pages 136-141, Jersey City, New
Jersey, September 2005.
(PDF)
- [ko2005x2]
- D. Ko and S. S. Bhattacharyya.
Dynamic configuration of dataflow graph topology for DSP system design.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-69-V-72, Philadelphia, Pennsylvania,
March 2005.
(PDF)
- [ko2005x3]
- D. Ko and S. S. Bhattacharyya.
Modeling of block-based DSP systems.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 40(3):289-299, July 2005.
(PDF)
- [sen2005x1]
- M. Sen, S. S. Bhattacharyya, T. Lv,
and W. Wolf.
Modeling image processing systems with homogeneous parameterized dataflow
graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-133-V-136, Philadelphia, Pennsylvania,
March 2005.
(PDF)
- [sen2005x2]
- M. Sen, I. Corretjer, F. Haim,
S. Saha, J. Schlessman, S. S. Bhattacharyya, and W. Wolf.
Computer vision on FPGAs: Design methodology and its application to gesture
recognition.
In Proceedings of the IEEE Workshop on Embedded Computer Vision,
pages CD-ROM version, 8 pages, San Diego, California, June 2005.
(PDF)
- [bamb2004x4]
- N. K. Bambha.
Communication-driven codesign for multiprocessor systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2004.
(PDF)
- [bamb2004x3]
- N. K. Bambha and S. S.
Bhattacharyya.
Interconnect synthesis for systems on chip.
In Proceedings of the IEEE International Workshop on System on Chip for
Real Time Processing, pages 263-268, Banff, Canada, July 2004.
(PDF)
- [bamb2004x1]
- N. K. Bambha, S. S. Bhattacharyya,
J. Teich, and E. Zitzler.
Systematic integration of parameterized local search in evolutionary
algorithms.
IEEE Transactions on Evolutionary Computation, 8(2):137-155,
April 2004.
(PDF)
- [bhat2004x1]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a module characterization approach for DSP software
optimization.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 38(2):131-146, September 2004.
(PDF)
- [chan2004x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model for multirate DSP applications.
IEEE Transactions on Signal Processing, 52(5):1209-1217, May
2004.
(PDF)
- [hsu2004x2]
- C. Hsu and S. S. Bhattacharyya.
Dataflow interchange format version 0.2.
Technical Report UMIACS-TR-2004-66, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2004.
Also Computer Science Technical Report CS-TR-4624.
(PDF)
- [hsu2004x1]
- C. Hsu, F. Keceli, M. Ko,
S. Shahparnia, and S. S. Bhattacharyya.
DIF: An interchange format for dataflow-based design tools.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, pages 423-432, Samos, Greece, July 2004.
(PDF)
- [kian2004x1]
- V. Kianzad and S. S.
Bhattacharyya.
CHARMED: A multiobjective cosynthesis framework for multi-mode embedded
systems.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 28-40, Galveston,
Texas, September 2004.
(PDF)
- [ko2004x2]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Compact procedural implementation in DSP software synthesis through recursive
graph decomposition.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 47-61, Amsterdam, The Netherlands,
September 2004.
(PDF)
- [ko2004x3]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Compact procedural synthesis of DSP software through recursive graph
decomposition.
Technical Report UMIACS-TR-2004-41, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2004.
Also Computer Science Technical Report CS-TR-4599.
(PDF)
- [murt2004x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Buffer merging --- a powerful technique for reducing memory requirements of
synchronous dataflow specifications.
ACM Transactions on Design Automation of Electronic Systems,
9(2):212-237, April 2004.
(PDF)
- [sen2004x1]
- M. Sen and S. S. Bhattacharyya.
Systematic exploitation of data parallelism in hardware synthesis of DSP
applications.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-229-V-232, Montreal, Canada, May 2004.
(PDF)
- [teic2004x1]
- J. Teich and S. S. Bhattacharyya.
Analysis of dataflow programs with interval-limited data-rates.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, pages 507-518, Samos, Greece, July 2004.
(PDF)
- [varm2004x1]
- A. Varma and S. S. Bhattacharyya.
Java-through-C compilation: An enabling technology for Java in embedded
systems.
In Proceedings of the Design Automation and Test in Europe Conference and
Exhibition, Designer's Forum, pages 161-167, Paris, France, February
2004.
(PDF)
- [bamb2003x1]
- N. K. Bambha, S. S. Bhattacharyya,
and G. Euliss.
Design considerations for optically connected systems on chip.
In Proceedings of the IEEE International Workshop on System on Chip for
Real Time Processing, pages 299-303, Calgary, Canada, June 2003.
(PDF)
- [bhat2003x1]
- S. S. Bhattacharyya,
E. Deprettere, and J. Teich, editors.
Domain-Specific Processors: Systems, Architectures, Modeling, and
Simulation.
Marcel Dekker, Inc., 2003.
(PDF)
- [hua2003x3]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Energy-efficient multi-processor implementation of embedded software.
In Proceedings of the International Workshop on Embedded Software,
pages 257-273, Philadelphia, Pennsylvania, October 2003.
(PDF)
- [hua2003x1]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Energy reduction techniques for multimedia applications with tolerance to
deadline misses.
In Proceedings of the Design Automation Conference, pages
131-136, Anaheim, California, June 2003.
(PDF)
- [hua2003x2]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Exploring the probabilistic design space of multimedia systems.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 233-240, San Diego, California, June 2003.
(PDF)
- [kian2003x1]
- V. Kianzad and S. S.
Bhattacharyya.
A comparison of clustering and scheduling techniques for embedded
multiprocessor systems.
Technical Report UMIACS-TR-2003-114, Institute for Advanced Computer Studies,
University of Maryland at College Park, December 2003.
Also Computer Science Technical Report CS-TR-4546.
(PDF)
- [ko2003x1]
- D. Ko and S. S. Bhattacharyya.
Modeling of block-based DSP systems.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 381-386, Seoul, Korea, August 2003.
(PDF)
- [ko2003x2]
- M. Ko and S. S. Bhattacharyya.
Data partitioning for DSP software synthesis.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 344-358, Vienna, Austria, September 2003.
(PDF)
- [loha2003x1]
- S. Lohani and S. S. Bhattacharyya.
Goal-driven reconfiguration of polymorphous architectures.
In S. S. Bhattacharyya, E. Depretter, and J. Teich, editors,
Domain-Specific Processors: Systems, Architectures, Modeling and
Simulation, pages 151-170. Marcel Dekker, Inc., 2003.
- [rine2003x1]
- M. Rinehart, V. Kianzad, and S. S.
Bhattacharyya.
A modular genetic algorithm for scheduling task graphs.
Technical Report UMIACS-TR-2003-66, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2003.
Also Computer Science Technical Report CS-TR-4497.
(PDF)
- [spiv2003x2]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
Logic foundry: Rapid prototyping for FPGA-based DSP systems.
EURASIP Journal on Applied Signal Processing, 2003(6):565-579,
May 2003.
(PDF)
- [spiv2003x1]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
Logic foundry: Rapid prototyping of FPGA-based DSP systems.
In Proceedings of the Asia South Pacific Design Automation
Conference, pages 374-381, Kitakyushu, Japan, January 2003.
(PDF)
- [bamb2002x3]
- N. Bambha and S. S. Bhattacharyya.
System synthesis for optically-connected, multiprocessors on-chip.
In W. Badawy and G. A. Julien, editors, System on Chip for Real-time
Systems, pages 339-448. Kluwer Academic Publishers, 2002.
(PDF)
- [bamb2002x4]
- N. Bambha and S. S. Bhattacharyya.
Techniques for co-design of optically-connected embedded multiprocessors.
In Proceedings of the Annual Workshop on High Performance Embedded
Computing, pages 97-99, Lexington, Massachusetts, September 2002.
(PDF)
- [bamb2002x1]
- N. Bambha, V. Kianzad,
M. Khandelia, and S. S. Bhattacharyya.
Intermediate representations for design automation of multiprocessor DSP
systems.
Journal of Design Automation for Embedded Systems, 7(4):307-323,
November 2002.
(PDF)
- [bhat2002x2]
- B. Bhattacharya and S. S.
Bhattacharyya.
Consistency analysis of reconfigurable dataflow specifications.
In E. F. Deprettere, J. Teich, and S. Vassiliadis, editors, Embedded
Processor Design Challenges, Lecture Notes in Computer Science, pages
1-17. Springer, 2002.
(PDF)
- [bhat2002x1]
- S. S. Bhattacharyya.
Hardware/software co-synthesis of DSP systems.
In Y. H. Hu, editor, Programmable Digital Signal Processors:
Architecture, Programming, and Applications, pages 333-378. Marcel
Dekker, Inc., 2002.
(PDF)
- [bhat2002x3]
- S. S. Bhattacharyya, E. Cheong,
J. Davis II, M. Goel, C. Hylands, B. Kienhuis, E. A. Lee, J. Liu, X. Liu,
L. Muliadi, S. Neuendorffer, J. Reekie, N. Smyth, J. Tsay, B. Vogel,
W. Williams, Y. Xiong, and H. Zheng.
Heterogeneous concurrent modeling and design in java.
Technical Report UCB/ERL M02/23, Department of Electrical Engineering and
Computer Sciences, University of California at Berkeley, August 2002.
(PDF)
- [chan2002x2]
- N. Chandrachoodan.
Performance Analysis and Hierarchical Timing for DSP System
Synthesis.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, August 2002.
(PDF)
- [chan2002x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. Ray Liu.
High-level synthesis of DSP applications using adaptive negative cycle
detection.
EURASIP Journal on Applied Signal Processing, 2002(9):893-907,
September 2002.
(PDF)
- [kece2002x1]
- F. Keceli, M. Ko, S. Shahparnia,
and S. S. Bhattacharyya.
First version of a dataflow interchange format.
Technical Report UMIACS-TR-2002-98, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2002.
Also Computer Science Technical Report CS-TR-4418.
(PDF)
- [loha2002x2]
- S. Lohani and S. S. Bhattacharyya.
Goal-driven reconfiguration of polymorphous architectures.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, Samos, Greece, July 2002.
(PDF)
- [loha2002x1]
- S. Lohani and S. S. Bhattacharyya.
System synthesis for polymorphous computing architectures.
Technical Report UMIACS-TR-2002-12, Institute for Advanced Computer Studies,
University of Maryland at College Park, February 2002.
Also Computer Science Technical Report CS-TR-4330.
(PostScript)
(PDF)
- [spiv2002x3]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
A component architecture for FPGA-based, DSP system design.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 41-51, San Jose,
California, July 2002.
(PDF)
- [spiv2002x1]
- G. Spivey, S. S. Bhattacharyya,
and Kazuo Nakajima.
Logic foundry: A rapid prototyping tool for FPGA-based DSP systems.
Technical Report UMIACS-TR-2002-29, Institute for Advanced Computer Studies,
University of Maryland at College Park, March 2002.
Also Computer Science Technical Report CS-TR-4349.
(PDF)
- [bamb2001x1]
- N. Bambha, S. S. Bhattacharyya,
J. Teich, and E. Zitzler.
Hybrid search strategies for dynamic voltage scaling in embedded
multiprocessors.
In Proceedings of the International Workshop on Hardware/Software
Co-Design, pages 243-248, Copenhagen, Denmark, April 2001.
(PDF)
- [bhat2001x2]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized dataflow modeling for DSP systems.
IEEE Transactions on Signal Processing, 49(10):2408-2421, October
2001.
(PDF)
- [bhat2001x3]
- S. S. Bhattacharyya, N. Bambha,
M. Khandelia, and V. Kianzad.
Mapping DSP applications onto self-timed multiprocessors.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, Pacific Grove, California, November 2001.
Invited paper.
(PDF)
- [chan2001x2]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
Adaptive negative cycle detection in dynamic graphs.
In Proceedings of the International Symposium on Circuits and
Systems, pages V-163-V-166, Sydney, Australia, May 2001.
(PDF)
- [chan2001x3]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
An efficient timing model for hardware implementation of multirate dataflow
graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, Salt Lake City, Utah, May 2001.
4 pages.
(PDF)
- [chan2001x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model.
In Proceedings of the International Symposium on Circuits and
Systems, pages V-367-V-370, Sydney, Australia, May 2001.
(PDF)
- [kian2001x2]
- V. Kianzad and S. S.
Bhattacharyya.
Multiprocessor clustering for embedded system implementation.
Technical Report UMIACS-TR-2001-52, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2001.
Also Computer Science Technical Report CS-TR-4272.
(PDF)
- [kian2001x1]
- V. Kianzad and S. S.
Bhattacharyya.
Multiprocessor clustering for embedded systems.
In Proceedings of the European Conference on Parallel Computing,
pages 697-701, Manchester, United Kingdom, August 2001.
(PDF)
- [murt2001x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared buffer implementations of signal processing systems using lifetime
analysis techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):177-198, February 2001.
(PDF)
- [bamb2000x1]
- N. K. Bambha and S. S.
Bhattacharyya.
A joint power/performance optimization technique for multiprocessor systems
using a period graph construct.
In Proceedings of the International Symposium on System Synthesis,
pages 91-97, Madrid, Spain, September 2000.
(PDF)
- [bamb2000x2]
- N. K. Bambha and S. S.
Bhattacharyya.
A period graph throughput estimator for multiprocessor systems.
Technical Report UMIACS-TR-2000-49, Institute for Advanced Computer Studies,
University of Maryland at College Park, July 2000.
Also Computer Science Technical Report CS-TR-4159.
(PDF)
- [bhat2000x4]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized dataflow modeling of DSP systems.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1948-1951, Istanbul, Turkey, June 2000.
(PDF)
- [bhat2000x1]
- B. Bhattacharya and S. S.
Bhattacharyya.
Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 84-89, Paris, France, June 2000.
(PDF)
- [bhat2000x3]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a useful annotation to aid block diagram compilers for
DSP.
In Proceedings of the International Symposium on Circuits and
Systems, pages IV-209-IV-212, Geneva, Switzerland, May 2000.
(PDF)
- [bhat2000x6]
- S. S. Bhattacharyya, R. Leupers,
and P. Marwedel.
Software synthesis and code generation for DSP.
IEEE Transactions on Circuits and Systems --- II: Analog and Digital
Signal Processing, 47(9):849-875, September 2000.
(PDF)
- [bhat2000x5]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP systems.
IEEE Transactions on Circuits and Systems --- I: Fundamental Theory and
Applications, 47(11):1597-1609, November 2000.
(PDF)
- [chan2000x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model for synchronous dataflow systems.
Technical Report UMIACS-TR-2000-75, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2000.
Also Computer Science Technical Report CS-TR-4198.
(PDF)
- [jaco2000x1]
- B. L. Jacob and S. S.
Bhattacharyya.
Real-time memory management: Compile-time techniques and run-time mechanisms
that enable the use of caches in real-time systems.
Technical Report UMIACS-TR-2000-60, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 2000.
Also Computer Science Technical Report CS-TR-4178.
(PDF)
- [khan2000x1]
- M. Khandelia and S. S.
Bhattacharyya.
Contention-conscious transaction ordering in embedded multiprocessor systems.
Technical Report UMIACS-TR-2000-09, Institute for Advanced Computer Studies,
University of Maryland at College Park, March 2000.
Also Computer Science Technical Report CS-TR-4109.
(PostScript)
(PDF)
- [khan2000x2]
- M. Khandelia and S. S.
Bhattacharyya.
Contention-conscious transaction ordering in embedded multiprocessors.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 276-285, Boston,
Massachusetts, July 2000.
(PDF)
- [murt2000x2]
- P. K. Murthy and S. S.
Bhattacharyya.
Buffer merging --- a powerful technique for reducing memory requirements of
synchronous dataflow specifications.
Technical Report UMIACS-TR-2000-20, Institute for Advanced Computer Studies,
University of Maryland at College Park, April 2000.
Also Computer Science Technical Report CS-TR-4126.
(PostScript)
(PDF)
- [murt2000x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared memory implementations of synchronous dataflow specifications.
In Proceedings of the Design, Automation and Test in Europe Conference
and Exhibition, pages 404-410, March 2000.
Paris, France.
(PDF)
- [murt2000x3]
- P. K. Murthy and S. S.
Bhattacharyya.
Systematic consolidation of input and output buffers in synchronous dataflow
specifications.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 673-682, Lafayette, Louisiana, October 2000.
(PDF)
- [srir2000x1]
- S. Sriram and S. S. Bhattacharyya.
Embedded Multiprocessors: Scheduling and Synchronization.
Marcel Dekker, Inc., 2000.
(PDF)
- [zitz2000x3]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Evolutionary algorithms for the synthesis of embedded software.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):452-456, August 2000.
(PDF)
- [zitz2000x1]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Multidimensional exploration of software implementations for DSP algorithms.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 24(1):83-98, February 2000.
(PostScript)
(PDF)
- [zitz2000x2]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Optimizing the efficiency of parameterized local search within global search: A
preliminary study.
In Proceedings of the Congress on Evolutionary Computation, pages
365-372, San Diego, California, July 2000.
(PDF)
- [bhat1999x9]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized modeling and scheduling of dataflow graphs.
Technical Report UMIACS-TR-99-73, Institute for Advanced Computer Studies,
University of Maryland at College Park, December 1999.
Also Computer Science Technical Report CS-TR-4083.
(PostScript)
(PDF)
- [bhat1999x3]
- S. S. Bhattacharyya.
Optimization trade-offs in the synthesis of software for embedded DSP.
In Proceedings of the International Workshop on Compiler and Architecture
Support for Embedded Systems, October 1999.
Washington, D. C.
(PostScript)
(PDF)
- [bhat1999x7]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a useful annotation to aid SDF compilers.
Technical Report UMIACS-TR-99-56, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4062.
(PostScript)
(PDF)
- [bhat1999x8]
- S. S. Bhattacharyya, R. Leupers,
and P. Marwedel.
Software synthesis and code generation for signal processing systems.
Technical Report UMIACS-TR-99-57, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4063.
(PostScript)
- [bhat1999x1]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Synthesis of embedded software from synchronous dataflow specifications.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 21(2):151-166, June 1999.
(PDF)
- [chan1999x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K.J. R. Liu.
Negative cycle detection in dynamic graphs.
Technical Report UMIACS-TR-99-59, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4065.
(PostScript)
- [murt1999x4]
- P. K. Murthy and S. S.
Bhattacharyya.
Approximation algorithms and heuristics for the dynamic storage allocation
problem.
Technical Report UMIACS-TR-99-31, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 1999.
Also Computer Science Technical Report CS-TR-4024.
(PDF)
- [murt1999x3]
- P. K. Murthy and S. S.
Bhattacharyya.
A buffer merging technique for reducing memory requirements of synchronous
dataflow specifications.
In Proceedings of the International Symposium on System Synthesis,
pages 78-84, San Jose, California, November 1999.
(PDF)
- [murt1999x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared memory implementations of synchronous dataflow specifications using
lifetime analysis techniques.
Technical Report UMIACS-TR-99-32, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 1999.
(PostScript)
- [teic1999x2]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
3D exploration of software schedules for DSP algorithms.
In Proceedings of the International Workshop on Hardware/Software
Co-Design, pages 168-172, May 1999.
Rome, Italy.
(PDF)
- [zitz1999x1]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Evolutionary algorithm based exploration of software schedules for digital
signal processors.
In Proceedings of the Genetic and Evolutionary Computation
Conference, pages 1762-1769, Orlando, Florida, July 1999.
(PDF)
- [zitz1999x4]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Optimized software synthesis for DSP using randomization techniques.
Technical report, Computer Engineering and Communication Networks Laboratory,
Swiss Federal Institute of Technology, Zurich, July 1999.
Revised version of teic1998x1.
(PostScript)
- [bhat1998x2]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP implementation --- part 1:
Maximum-throughput resynchronization.
Technical report, Digital Signal Processing Laboratory, University of Maryland,
College Park, July 1998.
(PostScript)
- [bhat1998x3]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP implementation --- part 2:
Latency-constrained resynchronization.
Technical report, Digital Signal Processing Laboratory, University of Maryland,
College Park, July 1998.
(PostScript)
- [teic1998x3]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Buffer memory optimization in DSP applications --- an evolutionary approach.
In Proceedings of the International Conference on Parallel Problem
Solving from Nature, pages 885-894, Amsterdam, The Netherlands,
September 1998.
(PostScript)
(PDF)
- [teic1998x1]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Optimized software synthesis for digital signal processing algorithms --- an
evolutionary approach.
Technical report, Computer Engineering and Communication Networks Laboratory,
Swiss Federal Institute of Technology, Zurich, January 1998.
(PostScript)
- [teic1998x2]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Optimized software synthesis for digital signal processing algorithms --- an
evolutionary approach.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 589-598, October 1998.
Boston, Massachusetts.
(PostScript)
(PDF)
- [bhat1997x2]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
APGAN and RPMC: Complementary heuristics for translating DSP block diagrams
into efficient software implementations.
Journal of Design Automation for Embedded Systems, 2(1):33-60,
January 1997.
(PDF)
- [bhat1997x1]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Optimizing synchronization in multiprocessor DSP systems.
IEEE Transactions on Signal Processing, 45(6):1605-1618, June
1997.
(PDF)
- [murt1997x1]
- P. K. Murthy, S. S. Bhattacharyya,
and E. A. Lee.
Joint minimization of code and data for synchronous dataflow programs.
Journal of Formal Methods in System Design, 11(1):41-70, July
1997.
(PDF)
- [bhat1996x5]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Software Synthesis from Dataflow Graphs.
Kluwer Academic Publishers, 1996.
(PDF)
- [bhat1996x2]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Latency-constrained resynchronization for multiprocessor DSP implementation.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 365-380, August 1996.
Chicago, Illinois.
(PostScript)
- [bhat1996x1]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Self-timed resynchronization: A post-optimization for static multiprocessor
schedules.
In Proceedings of the International Parallel Processing Symposium,
pages 199-205, April 1996.
Honolulu, Hawaii.
(PostScript)
- [bhat1995x3]
- S. S. Bhattacharyya, J. T. Buck,
S. Ha, and E. A. Lee.
Generating compact code from dataflow specifications of multirate signal
processing algorithms.
IEEE Transactions on Circuits and Systems --- I: Fundamental Theory and
Applications, 42(3):138-150, March 1995.
(PostScript)
- [bhat1995x7]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Converting graphical DSP programs into memory-constrained software
prototypes.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 194-200, Chapel Hill, North Carolina, June 1995.
(PDF)
- [bhat1995x1]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Optimal parenthesization of lexical orderings for DSP block diagrams.
In Proceedings of the International Workshop on VLSI Signal
Processing, pages 177-186. IEEE press, October 1995.
Sakai, Osaka, Japan.
(PDF)
- [bhat1995x8]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Renesting single appearance schedules to minimize buffer memory.
Technical report, Electronics Research Laboratory, University of California at
Berkeley, April 1995.
(PDF)
- [pino1995x3]
- J. L. Pino, S. S. Bhattacharyya,
and E. A. Lee.
A hierarchical multiprocessor scheduling framework for synchronous dataflow
graphs.
Technical report, Electronics Research Laboratory, University of California at
Berkeley, May 1995.
(PDF)
- [pino1995x2]
- J. L. Pino, S. S. Bhattacharyya,
and E. A. Lee.
A hierarchical multiprocessor scheduling system for DSP applications.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, pages 122-126 vol.1, Pacific Grove, California, November
1995.
(PostScript)
(PDF)
- [bhat1994x3]
- S. S. Bhattacharyya.
Compiling Dataflow Programs for Digital Signal Processing.
PhD thesis, Department of Electrical Engineering and Computer Sciences,
University of California at Berkeley, July 1994.
(PDF)
- [bhat1994x2]
- S. S. Bhattacharyya and E. A. Lee.
Looped schedules for dataflow descriptions of multirate signal processing
algorithms.
Journal of Formal Methods in System Design, pages 183-205,
December 1994.
(PDF)
- [bhat1994x1]
- S. S. Bhattacharyya and E. A. Lee.
Memory management for dataflow programming of multirate signal processing
algorithms.
IEEE Transactions on Signal Processing, 42(5):1190-1201, May
1994.
(PDF)
- [murt1994x3]
- P. K. Murthy, S. S. Bhattacharyya,
and E. A. Lee.
Combined code and data minimization for synchronous dataflow programs.
Technical Report M94/93, Department of Electrical Engineering and Computer
Sciences, University of California at Berkeley, November 1994.
(PostScript)
- [murt1994x2]
- P. K. Murthy, S. S. Bhattacharyya,
and E. A. Lee.
Minimizing memory requirements for chain-structured synchronous dataflow
programs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 453-456 vol.2, Adelaide, SA, Australia,
April 1994.
(PDF)
- [bhat1993x1]
- S. S. Bhattacharyya and Edward A.
Lee.
Scheduling synchronous dataflow graphs for efficient looping.
Journal of VLSI Signal Processing, 6(3):271-288, December 1993.
(PDF)